************************************************************************ ************************************************************************ ** ** ** Application notes for PMC devices ** ** ** ** (Informal Document) ** ** ** ** To find the application notes for your device search for the ** ** 'core' part name. As an example using the 25LV010 8 pin SOIC ** ** you would search this document for the entry "25LV010" ** ** ** ************************************************************************ ************************************************************************ ************************************************************************ 25LV512 ---------- 25LV010 ---------- 25LV040 ---------- There are four levels of Block Protection that can be supported on these devices: Start/End Block (BP1), (BP0) Protection Addresses Security Fuse settings: SF2, SF1 25LV512 25LV010 ------------------------------------ ------------ -------------- 0, 0 None None 0, 1 None $18000->$1FFFF 1, 0 None $10000->$1FFFF 1, 1 $0000->$FFFF $00000->$1FFFF ------------------------------------ ------------ --------------- Start/End Block (BP2), (BP1), (BP0) Protection Addresses Security Fuse settings: SF3, SF2, SF1 25LV040 ------------------------------------------- -------------------- 0 0 0 none 0 0 1 $70000->$7FFFF 0 1 0 $60000->$7FFFF 0 1 1 $40000->$7FFFF 1 0 0 $00000->$3FFFF 1 0 1 $00000->$3FFFF 1 1 0 $00000->$3FFFF 1 1 1 $00000->$3FFFF ------------------------------------------- --------------------- NOTE: The "Erase EE device" option must be enabled when re-programming the device in order to remove the Block Protection. To program the Hardware Write Protection option enable the "Program protect reg." flag. Performing a Load operation will also load the Status Register Protection Bits into the following address locations in User RAM: 25LV512 = Address $10000 25LV010 = Address $20000 25LV040 = Address $80000 The data format in the Programmer's User RAM will follow the same format as defined in the corresponding device's data sheet. Status Register Format in relation to the Protection Bits: -------------------------------------------------------- | Bit 7 |Bit 6 |Bit 5 |Bit 4 |Bit 3 |Bit 2 |Bit 1 |Bit 0 | |--------------------------------------------------------| | WPBEN | X | X | BP2 | BP1 | BP0 | X | X | -------------------------------------------------------- ************************************************************************ ************************************************************************